? semiconductor components industries, llc, 2008 march, 2008 - rev. 8 1 publication order number: nb100lvep224/d nb100lvep224 2.5v/3.3v 1:24 differential ecl/pecl clock driver with clock select and output enable description the nb100lvep224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. the part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. the two clock inputs are differential ecl/pecl and they are selected by the clk_sel pin. to avoid generation of a runt clock pulse when the device is enabled/disabled, the output enable (oe ) is synchronous ensuring the outputs will only be enabled/disabled when they are already in low state (see figure 4). the nb100lvep224 guarantees low output-to-output skew. the optimal design, layout, and processing minimize skew within a device and from lot to lot. in any differential output, the same bias and termination scheme is required. unused output pairs should be left unterminated (open) to reduce power and switching noise as much as possible. any unused single line of a differential pair should be terminated t he same as the used line to maintain balanced loads on the differential driver outputs. the wide vihcmr specification allows both pair of clock inputs to accept lvds levels. the nb100lvep224, as with most other ecl devices, can be operated from a positive v cc supply in lvpecl mode. this allows the lvep224 to be used for high performance clock distribution in +3.3 v or +2.5 v systems. single-ended clk input operation is limited to a v cc 3.0 v in lvpecl mode, or v ee -3.0 v in necl mode. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. for more information on pecl terminations, designers should refer to application note and8020/d. features ? 20 ps typical output-to-output skew ? 75 ps typical device-to-device skew ? maximum frequency > 1 ghz ? 650 ps typical propagation delay ? lvpecl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = -2.375 v to -3.8 v ? internal input pulldown resistors ? q output will default low with inputs open or at v ee ? thermally enhanced 64-lead lqfp ? clock inputs are lvds-compatible; requires external 100 lvds termination resistor ? pb-free packages are available* *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. lqfp-64 fa suffix case 848g marking diagram* *for additional marking information, refer to application note and8002/d. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information a = assembly location wl = wafer lot yy = year ww = work week g = pb-free package nb100 lvep224 awlyywwg 64 1
nb100lvep224 http://onsemi.com 2 49 50 51 52 53 54 55 56 31 30 29 28 27 26 25 12345678 48 47 46 45 44 43 42 41 32 all v cc , v cco , and v ee pins must be externally connected to appropriate power supply to guarantee proper operation. the thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of tran sfer\ ring 1.2 watts. this exposed pad is electrically connected to v ee internally. oe (1) l l h h table 1. pin description function ecl differential input clock ecl differential input clock ecl input clk select ecl output enable ecl differential outputs positive supply negative supply pin clk0*, clk0** clk1*, clk1** clk_sel* oe* q0-q23, q0-q23 v cc , v cco v ee *** figure 1. 64-lead lqfp pinout (top view) v cco clk0 clk0 clk_sel clk1 clk1 v ee oe v ee v ee q8 q8 q9 q9 q10 q10 q7 v cco q7 q6 q6 q5 q1 v cco v cco q15 q15 q16 q16 q17 q17 v cco clk_sel l h l h q0-q23 q0-q23 clk0 clk1 l l clk0 clk1 h h 1. the oe (output enable) signal is synchronized with the falling edge of the lvpecl_clk signal. nb100lvep224 * pins will default low when left open. ** pins will default high when left open. *** the thermally conductive exposed pad on the bottom of the package is electrically connected to v ee internally. 9 10111213141516 q0 q0 v cc q23 q23 v cco q22 q22 q18 q18 q19 q19 q20 q20 q21 q21 23 22 21 20 19 18 17 24 40 39 38 37 36 35 34 33 57 58 59 60 61 62 63 64 q11 q11 q12 q12 q13 q13 q14 q14 q5 q4 q4 q3 q3 q2 q2 q1 table 2. function table
nb100lvep224 http://onsemi.com 3 0 1 figure 2. logic diagram clk_sel clk0 clk0 clk1 clk1 oe q0-q23 q0-q23 q d 24 24 v cc v ee table 3. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 150 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 2) pb pkg pb-free pkg lqfp-64 level 2 level 3 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 654 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, refer to application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v -6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 to 0 -6 to 0 v t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (see application information) 0 lfpm 500 lfpm 64 lqfp 64 lqfp 35.6 30 c/w c/w jc thermal resistance (junction-to-case) (see application information) 0 lfpm 500 lfpm 64 lqfp 64 lqfp 3.2 6.4 c/w c/w t sol wave solder pb pb-free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nb100lvep224 http://onsemi.com 4 table 5. lvpecl dc characteristics v cc = 2.5 v; v ee = 0 v (note 3) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 130 160 195 135 165 200 140 165 205 ma v oh output high voltage (note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 4) 555 680 900 555 680 900 555 680 900 mv v ih input high voltage (single-ended) (note 5) 1335 1620 1335 1620 1275 1620 mv v il input low voltage (single-ended) (note 5) 555 900 555 900 555 900 mv v ihcmr input high voltage common mode range (differential configuration) (note 6) clk/clk 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. input and output parameters vary 1:1 with v cc . v ee can vary + 0.125 v to -1.3 v. 4. all outputs loaded with 50 to v cc - 2.0 v. see figure 6. 5. do not use v bb at v cc < 3.0 v. 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren\ tial input signal. table 6. lvpecl dc characteristics v cc = 3.3 v; v ee = 0 v (note 7) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 140 165 195 145 175 205 145 175 210 ma v oh output high voltage (note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 8) 1355 1480 1700 1355 1480 1700 1355 1480 1700 mv v ih input high voltage (single-ended) (note 9) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single-ended) (note 9) 1355 1700 1355 1700 1355 1700 mv v ihcmr input high voltage common mode range (differential configuration) (note 10) (figure 5) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to -0.5 v. 8. all outputs loaded with 50 to v cc - 2.0 v. see figure 6. 9. single ended input operation is limited v cc 3.0 v in lvpecl mode. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep224 http://onsemi.com 5 table 7. necl dc characteristics v cc = 0 v, v ee = -2.375 v to -3.8 v (note 11) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current v ee = -2.5 v v ee = -3.3 v 130 140 160 165 195 195 135 145 165 175 200 205 140 145 165 175 205 210 ma v oh output high voltage (note 12) -1145 -1020 -895 -1145 -1020 -895 -1145 -1020 -895 mv v ol output low voltage (note 12) -1945 -1820 -1600 -1945 -1820 -1600 -1945 -1820 -1600 mv v ih input high voltage (single-ended) (note 13) -1165 -880 -1165 -880 -1165 -880 mv v il input low voltage (single-ended) (note 13) -1945 -1600 -1945 -1600 -1945 -1600 mv v ihcmr input high voltage common mode range (differential configuration) (note 14) (figure 5) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. input and output parameters vary 1:1 with v cc . 12. all outputs loaded with 50 to v cc - 2.0 v. see figure 6. 13. single ended input operation is limited v ee -3.0 v in necl mode. 14. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 8. ac characteristics v cc = 2.375 v to 3.8 v; v ee = 0 v (note 15) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max v opp differential output voltage (figure 3) f out < 50 mhz f out < 0.8 ghz f out < 1.0 ghz 600 600 600 750 750 700 600 600 525 725 725 650 575 550 400 700 650 525 mv mv mv t plh t phl propagation delay (differential configuration) clkx-qx clk_selx-qx 500 600 600 700 700 800 550 650 650 800 750 900 650 750 750 850 1000 1150 ps ps t skew within-device skew (note 16) device-to-device skew (note 17) 20 50 40 300 20 50 40 300 35 100 60 300 ps ps t jitter random clock jitter (figure 3) (rms) 1 5 1 5 1 5 ps v pp input swing (differential configuration) (note 19) (figure 5) 200 800 1200 200 800 1200 200 800 1200 mv t s oe set up time (note 18) 200 200 200 ps t h oe hold time 200 200 200 ps t r /t f output rise/fall time (20%-80%) 100 200 300 100 200 300 150 250 350 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 15. measured with pecl 750 mv source, 50% duty cycle clock source. all outputs loaded with 50 to v cc - 2.0 v. see figure 6. 16. skew is measured between outputs under identical transitions and conditions on any one device. 17. device-to-device skew for identical transitions at identical v cc levels. 18. oe set up time is defined with respect to the falling edge of the clock. oe high-to-low transition ensures outputs remain disabled during the next clock cycle. oe low-to-high transition enables normal operation of the next input clock. 19. v pp is the differential input voltage swing required to maintain ac characteristics including t pd and device-to-device skew.
nb100lvep224 http://onsemi.com 6 figure 3. output amplitude (v opp ) versus input frequency and random clock jitter (t jitter ) input frequency (ghz) 0.5 0.6 0.7 0.8 1.3 1.5 800 900 700 600 500 400 300 200 output amplitude (mv) 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 10 rms jitter (ps) q amp (mv) rms jitter (ps) 1.0 0.9 1.4 1.2 1.1 2.5 v 3.3 v figure 4. output enable (oe) timing diagram clk clk oe q q figure 5. lvpecl differential input levels v ih (diff) v il (diff) v ee v cc (lvpecl) v ihcmr v pp figure 6. typical termination for output driver and device evaluation (see application note and8020/d - termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc - 2.0 v
nb100lvep224 http://onsemi.com 7 applications information using the thermally enhanced package of the nb100lvep224 the nb100lvep224 uses a thermally enhanced 64-lead lqfp package. the package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. this exposed metal pad will provide the low thermal impedance that supports the power consumption of the nb100lvep224 high-speed bipolar integrated circuit and will ease the power management task for the system design. in multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the nb100lvep224. the size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. however, the solderable area should be at least the same size and shape as the exposed pad on the package. direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. the thermal vias will connect the exposed pad of the package to internal copper planes of the board. the number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. the recommended thermal land design for nb100lvep224 applications on multi-layer boards comprises a 4 x 4 thermal via array using a 1.2 mm pitch as shown in figure 7 providing an efficient heat removal path. figure 7. recommended thermal land pattern all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 the via diameter should be approximately 0.3 mm with 1oz. copper via barrel plating. solder wicking inside the via may result in voiding during the solder process and must be avoided. if the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. this will supply enough solder paste to fill those vias and not starve the solder joints. the attachment process for the exposed pad package is equivalent to standard surface mount packages. figure 8, recommended solder mask openings, shows a recommended solder mask opening with respect to a 4 x 4 thermal via array. because a lar ge solder mask opening may result in a poor rework release, the opening should be subdivided as shown in figure 8. for the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. figure 8. recommended solder mask openings all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 0.2 1.0 1.0 0.2 proper thermal management is critical for reliable system operation. this is especially true for high-fanout and high output drive capability products. for thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: table 9. thermal resistance * lfpm ja c/w jc c/w 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * junction to ambient and junction to board, four-conductor layer test board (2s2p) per jesd 51-8 these recommendations are to be used as a guideline, only. it is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. the exposed pad of the nb100lvep224 package is electrically shorted to the substrate of the integrated circuit and v ee . the thermal land should be electrically connected to v ee .
nb100lvep224 http://onsemi.com 8 ordering information device package shipping ? nb100lvep224fa lqfp-64 160 units / tray NB100LVEP224FAG lqfp-64 (pb-free) 160 units / tray nb100lvep224far2 lqfp-64 1500 / tape & reel nb100lvep224farg lqfp-64 (pb-free) 1500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d - ecl clock distribution techniques an1406/d - designing with pecl (ecl at +5.0 v) an1503/d - eclinps i/o spice modeling kit an1504/d - metastability and the eclinps family an1568/d - interfacing between lvds and ecl an1672/d - the ecl translator guide and8001/d - odd number counters design and8002/d - marking and date codes and8020/d - termination of ecl logic devices and8066/d - interfacing with eclinps and8090/d - ac characteristics of ecl devices
nb100lvep224 http://onsemi.com 9 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: mm. 3. datum plane ?e? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting plane. 4. datum ?x?, ?y? and ?z? to be determined at datum plane datum ?e?. 5. dimensions m and l to be determined at seating plane datum ?t?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum pland ?e?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum d dimension by more than 0.08 (0.003). dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). 8. exact shape of each corner is optional. dim a min max min max inches 10.00 bsc 0.394 bsc millimeters b 10.00 bsc 0.394 bsc c 1.35 1.45 0.053 0.057 d 0.17 0.27 0.007 0.011 f 0.45 0.75 0.018 0.030 g 0.50 bsc 0.020 bsc h 1.00 ref 0.039 bsc j 0.09 0.20 0.004 0.008 k 0.05 0.15 0.002 0.006 l 12.00 bsc 0.472 bsc m 12.00 bsc 0.472 bsc n 0.20 0.008 p 0 7 0 7 r 0 --- 0 --- s --- 1.60 --- 0.063 v w aa 0.17 0.23 0.007 0.009 ab 0.09 0.16 0.004 0.006 ac 0.08 --- 0.003 --- ad 0.08 --- 0.003 --- ae 4.50 4.78 0.180 0.188 0.05 (0.002) s 1 b b/2 16 17 32 33 48 49 64 -x- l l/2 -z- m m/2 a a/2 aj aj z 0.20 (0.008) t x-y 4 pl z 0.20 (0.008) e x-y -t- seating plane g/2 g 4 pl ag ag d 64 pl z 0.08 (0.003) m t x-y -e- 0.08 (0.003) t exposed pad view ag-ag detail ah detail ah ???? ???? aa d ab j detail aj-aj ref base metal plating z 0.08 (0.003) m y t-u s c k v r w n f h p ac 0.25 gage plane 60 pl 1 16 17 32 33 48 49 64 ad --- --- 11 13 11 13 11 13 11 13 af 4.50 4.78 0.180 0.188 ae af lqfp 64 lead exposed pad 848g-02 issue a
nb100lvep224 http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 nb100lvep224/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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